Their "7 nm" relied on multi patterning DUV which leads to restrictive design rules, more steps and masks and lower yields, which is why I put it in quotes and said it's uncompetitive.
The last DUV node was 10 nm, that's the best logic node they have which is comparable to TSMC/Samsung/Intel's 10 nm.
https://en.wikipedia.org/wiki/7_nm_process
not too shabby of a fall-back.