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> (e.g. in a 3D chip it can be quite difficult to distribute a high speed, high quality/low skew+jitter clock)

How thick is "3D" here, and why is that? What makes a bit of vertical distance harder than several mm of horizontal distance?



Maybe the electrons need to wait for the elevator?


It's hard more due to EDA tool reasons than due to physical reasons :)

Which incidentally, is also the main reason why asynchronous logic isn't more popular.


I believe troubles are caused by induction effect from adjacent layer (similar to self-inductance[0]).

[0] - https://en.wikipedia.org/wiki/Inductance#Self-inductance_of_...


Not just inductance, but capacitance between the layers themselves too since you've got to have an insulator between them. All the fun things you get in 2d from nanometer scale devices are now compounded in another degree of freedom. The only thing I don't think you have to work around is quantum tunneling between layers because they'll probably be too far apart still to need that level of work.




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